1. Field of the Invention
The present invention relates to a method and a related circuit for providing an output clock, and more particularly, a method and related circuit for providing an output clock along a data path according to a reference clock.
2. Description of the Prior Art
In the information-oriented society, various kinds of data are processed, transmitted and stored rapidly and effectively in the digital mode. Digital signal circuits used to process digital signals become one of the fundamental blocks of modern information systems.
As known by those skilled in the art, digital signal circuits are triggered by clocks to process and transmit sequential digital signals and to synchronize timing of function blocks. Due to the increasing complexity of digital signal circuits, parameters and functions of circuits require more careful design. Please refer to FIG. 1 and FIG. 2. FIG. 1 and FIG. 2 illustrate conventional digital signal circuits 10 of different implementation methods. As shown in FIG. 1, to complete functions of ordinary digital signal circuits, the signal circuit 10 comprises a logic array 12, a plurality of flip-flops 14A and 14B, and a clock control circuit 16. The clock control circuit 16 generates a reference clock 18B according to a source clock 18A; the source clock 18A can be generated by the oscillator in the signal circuit 10, or be fed by other oscillation circuits outside the signal circuit 10. Each flip-flop 14A, 14B comprises an input port 13A, an output port 13B, and a clock port 15. Input port 13A receives input signals (as two different input data from two input ports), clock port 15 receives the triggering signal, and the flip-flops 14A, 14B, triggered by clocks of clock port 15, change output signals of output port 13B according to signals of input port 13A (as two different output data of two output ports). The rising edge of the clock signal from clock port 15 triggers flip-flop 14A, leading to data transition in the output signals of output port 13B while the falling edge of the clock signal from clock port 15 triggers flip-flop 14B, resulting in data transition in the output signals of output port 13B. The logic array 12 comprises several kinds of logic gates, such as AND gate 19A and OR gate 19B in FIG. 1. Proper connection of input ports/output ports of flip-flops 14A and 14B as well as logic gates of logic array 12 facilitates implementation of different functions of digital signal circuits, such as adders, timers, state machines, etc. In addition, the signal circuit 10 comprises a plurality of output pads 22. For example, the signal circuit 10 can be enclosed in a package, with each output pad 22 being a pin extending outside the package. Thus, output signals of logic gates in logic array 12 or flip-flop output ports can be sent outside the signal circuit 10 by theses output pads 22. Output ports of the flip-flops and outputs of the logic gates in the logic array 12 are taken as data paths of output signals of the signal circuit 10, and each output port becomes a transmission medium of a data path of the signal circuit 10.
Relative to the data path, the transmission path, through which the clock control circuits 16 is connected to each clock port of the flip-flop is called a clock path. As the mentioned before, to align the timing of the flip-flops 14A and 14B, both flip-flops 14A and 14B should be triggered by reference clock 18B. In other words, to consider the logic function only, clock ports 15 of flip-flops 14A and 14B should be connected to control circuits 16 directly, as shown in FIG. 1. When all flip-flops are triggered by the reference clock 18B, output signals of these flip-flops will start data transition simultaneously. Since signals in the data path and the reference clock in the clock path are synchronous in logic, they can be used in logical operations, so that signals in the data path can change according to the reference clock 18B. As shown in FIG. 1, a signal 20 can undergo an OR operation with reference clock 18B by the OR gate 19B and signals in the data path of output of the OR gate 19B will relate to the reference clock 18B.
However, including the non-ideal effects of actual circuits, the signal circuit 10, as shown in FIG. 2, should include a buffer 24 in front of each flip-flop to which the clock 18B is transmitted so that the rising edge or the falling edge of clock signals transmitted to clock ports 15 of flip-flops 14A and 14B can actually trigger each flip-flop at the same time. When the digital circuit is operating, flip-flops 14A and 14B are equivalent to a capacitive load of clock control circuits 16. Considering the branches 26A to 26C of the clock path shown in FIG. 2, there are three flip-flops in branch 26A, four flip-flops in branch 26B, and two in branch 26C. The capacitive load of branch 26B is the largest, and that of branch 26C is the smallest. If flip-flops in these two branches are driven by clocks of the same strength, the clock transmitted to branch 26B becomes late when it compared to the clock transmitted to branch 26C. The clock of branch 26B is delayed because the larger capacitive load of branch 26B increases the charging or discharging time. Therefore, as shown in FIG. 2, more buffers 24 (or buffers with stronger driving ability) should be connected in branch 26B to increase the driving strength of the clock and overcome the non-ideal operation caused by larger capacitance so that timing of clocks triggering each flip-flop is correct.
To consider the non-ideal nature of actual digital signal circuits, time response of flip-flops triggered by clocks should be considered besides adjusting the driving ability of each clock path of the reference clock 18B. As for this situation, please refer to FIG. 3. FIG. 3 illustrates a timing diagram of input/output signals of a conventional rising-edge-triggered flip-flop 14 when the flip-flop 14 is triggered by the reference clock 18B. The flip-flop 14, triggered by the reference clock 18B, receives a signal 28A from one input port (marked as D in FIG. 3) and outputs a signals 28B from one output port (marked as Q in FIG. 3). FIG. 3 plots waveforms of signals 28A, 28B and signal level of reference clock 18B versus time; the x-axis represents time and the y-axis represents magnitude of waveform level. As shown in FIG. 3, when the reference clock 18B triggers the flip-flop 14 at rising edges at time points tp0, tp1, tp2 and tp3, the flip-flop 14 will sample different levels of signals 28A at these time points and change waveform levels of the corresponding output signal 28B. Thus, signal levels of the output signal 28B at time points tp0, tp1, tp2 and tp3 equal waveform levels of input signal 28A at these time points. For example in FIG. 3, levels of signal 28A at time points tp0, tp1, tp2 and tp3 are H, H, H, and L, respectively, so signal levels of output signal 28B at these time are H, H, H and L. However, in the real case, to make sure that flip-flops 14 are able to sample the stable level of input signal 28A according to triggering of the rising edge of reference clock 18B, data transition of signal 28A should be earlier than the rising edge of reference clock 18B. For example, as shown in FIG. 3, if the flip-flop 14 is required to sample level H of input signal 28A at time tp0, the data transition of input signal 28A, from level L to level H, should be at time as early as time tpA. In other words, there needs to be a time between data transition of input signal 28A and rising edge of clock 18B, and this time is called the set-up time.
After rising edge of reference clock 18B occurs, the input signal 28A at least maintains its level for a period of time so that the flip-flop 14 can sample data correctly; the time for which the signal 28A maintains its level after the rising edge is called the hold time. For example, in FIG. 3, the flip-flop 14 samples data at time tp2, and data transition of the input signal 28A occurs until time tpB so that the flip-flop 14 can stably sample the level of signal 28A at time tp2. In summary, in designing the signal circuit 10, besides considering the correct logic operation of the signal circuit 10 in FIG. 1, the actual operation in FIG. 2 should also be considered. This operation in FIG. 2 includes properly fine-tuning the driving strength of the clock in each branch of the clock path, and inducing a period of time between data transition of input signals of flip-flops and rising edges (or the falling edges) of clocks (the period of time can be fine-tuned by delay of buffers). Today, functions of digital signal circuits have become more complicated, so circuit designs in FIG. 1 and FIG. 2 are assisted and implemented by software tools and computers. The logic design of FIG. 1 can be simulated by programming languages, such as VHDL; the clock design of FIG. 2 can be aided by a tool such as a “clock tree synthesizer”.
As mentioned before, the signal circuit 10 is required to do logical operations between reference clock 18B and signal 20 by logic gates in logic array 12 so that data in the data path of logic array 12 relate to reference clock 18B. As shown in FIG. 1 and FIG. 2, reference clock 18B performs a logic operation with signal 20 in logic gate 19B. However, to consider actual operation of digital signal circuits, there should be a proper period between the time when data transition of signals in each data path occurs and the time when rising edge (or the falling edge )in reference clock 18B occurs. If the reference clock 18B in the clock path and the signals in the data path undergo logic operations directly, logic operations between the time of two data transitions may not be as expected, resulting in distortion in a logic operation. In addition, when a software tool such as a “clock tree synthesizer” assists in the design of the signal circuit 10, this tool can neglect adjusting the driving ability of the reference clock 18B in the branch of logic gate 19B because the reference clock 18B is directly input to the logic gate 19B. The clock tree synthesizer will recognize signals connected to each clock port of the flip-flops as a clock and automatically adjust the ability and delay of the clocks, but the tool cannot recognize signals input to the logic gate 19B as a clock, so the driving ability and delay of the reference clock 18B directly input into the logic gate 19B cannot be adjusted automatically. This causes rising edges or falling edges of the clock in the branch of the logic gate 19B and those of input clocks of flip-flops in the branches 26A to 26C to not occur at the same time.
In addition, as known by those skilled in the art, to check if the logic design of the signal circuit 10 can implement the desired functions, the signal circuit 10 can be simulated by computers. Logic design in FIG. 1 is to examine the functions of the signal circuit 10. However, in simulation of logic functions, the clocks of the flip-flops are assumed to be synchronous. No matter how high the capacitive load in the branches of flip-flops, a simulation assumes rising edges and falling edges of clocks in each clock port of flip-flops to happen at the same time because the purpose of the simulation is to simulate the logic function. However, if the logic gate 19B performs an operation directly on the reference clock 18B and the signal 20, the simulation will not take reference clock 18B input to the logic gate 19B as the clock of the flip-flops, but recognize the reference clock 18B input to the logic gate 19B as output signals of the clock control circuits 16. Thus, the simulation tool considers that the reference clock 18B input into the logic gate 19B and the clock of each clock port of the flip-flops are not synchronous, leading to failure of a correct simulation and increasing difficulty of logic function confirmation of the signal circuit 10.
In summary, in the signal circuit 10, there are often logic operations between the reference clock and other signals, so that results of logic operations directly relate to timing of the reference clock. Even in some special circuits, such as a field programmable gate array, the clock cannot be output directly from output pads, but through a data path of a logic array and flip-flops. However, as discussed before, in the prior art, if the clock in the clock path directly performs logic operations, there will be much difficulty in operation and design of the circuits, so it is difficult for circuit designers to control clocks after logic operations.
Besides, in modern digital signal circuits, signals are often exchanged between circuits of different frequencies. Please refer to FIG. 4. FIG. 4 illustrates each relative signal in a signal circuit 30 when a signal 36 is transmitted between two circuit modules 32A and 32B of different clocks. In the signal circuit 30, the circuit module 32A is working with the clock 34A, and the circuit module 32B is working at a clock 34B, whose frequency is twice that of the clock 34A. In the prior art, when the circuit module 32A transmits the signal 36 to the circuit module 32B, the circuit module 32B transforms the signals 36 to a signal 38 and finally produces a signal 40 so that circuit module 32B can recognize the signal 36. FIG. 4 illustrates a waveform-timing diagram of these related signals. The x-axis represents time, and the y-axis represents magnitude of signal level. In the example of FIG. 4, because the frequency of the clock 34B of the circuit module 32B is double that of the clock 34A of the circuit module 32A, the period of clock 34A is twice of that of the clock 34B. As shown in FIG. 4, one period of the clock 34A between time points tp4 and tp6 equals two periods of clock 34B between time points tp4 and tp5 and between time points tp5 and tp6. Triggered by the clocks, the signals of each circuit module correspond to periods of these circuit modules. As in the example of FIG. 4, in the circuit module 32A, the signal 36 between time points tp4 and tp6 (corresponding to a period of clock 34A) maintains a level H, and is taken as digital data “1”. Similarly, the signal 36 between time points tp6 and tp8 (corresponding to another period of the clock 34A) maintains a level L, and is taken as a digital data “0”.
When the circuit module 32A transmit signal 36 to the circuit module 32B which has double the frequency, signals 36 should be processed and transformed properly due to different working frequencies of the two circuit modules so that the circuit module 32B reads data of the signal 36 correctly. Without transforming the signal 36, the circuit module 32A working in the double frequency will recognize one digital data “1” of signal 36 corresponding to the clock 34A as two digital data “1” corresponding to clock 34B thereby misreading the data in signal 36. The method of transforming data in the signal 36 according to the prior art is described as follows. In the prior art, after the circuit module 32B receives the signal 36, the signal 38 can be produced according to the signal 36 if rising-edge-triggered flip-flops are triggered by the clock 34B. This delays signal 38 for a period of clock 34B in comparison with signal 36. Then, signal 36 undergoes an AND operation with inversion of the signal 38 and the signal 40 is generated. Thus, the signal 40 will keep the level H for the time between points tp4 and tp5 corresponding to a period of clock 34B. Therefore the circuit module 32B is able to recognize the data as one digital data “1”. In other words, there is one digital data “1” of the signal 36 in clock 34A, and after the signal 36 is transformed to the signal 40, the signal 40 corresponding to the clock 34B will have one digital data “1”. After the signal 36 of the circuit module 32A is transformed to the signal 40, it can be recognized correctly by the circuit module 32B working at double the frequency.
However, there are some disadvantages in the prior art described above. Circuits made in accordance with the prior art cannot process burst data. Regarding this situation, please refer to FIG. 5. FIG. 5 illustrates waveform timing diagrams of each relative signal when the two circuit modules 32A and 32B of the digital circuit 30 in FIG. 4 transmit a signal 42. The x-axis represents time, and the y-axis represents magnitude of waveform. As shown in FIG. 5, signal 42 in the circuit module 32A continuously keeps at a level H during time points tp9 to tp11 (corresponding to two periods of clock 34A). The signal is equivalent to two continuous digital data “1”. If, in prior art, flip-flops are triggered by the clock 34B to produce the signal 46, and inversion of the signal 46 undergoes an AND operation with the signal 42 to output a signal 48, there is still one digital data “1” corresponding to one period of the clock 34B in the signal 48. In other words, the data transmitted from the circuit module 32A to the circuit module 32B cannot be burst data according to the method of the prior art. This decreases the efficiency of data transmission between the two circuit modules.